FIG. 1 depicts, in circuit diagram form, a portion of an output buffer 100 known in the prior art. An output pin 102 is connected to a first current electrode of an n-type or n-channel transistor 104. A control electrode of transistor 104 is coupled to a first voltage supply, labeled OVDD. A second current electrode of transistor 104 is coupled to a first current electrode of an n-type transistor 106. A control electrode of transistor 106 receives an input signal, labeled DATA. A second current electrode of transistor 104 is coupled to a second voltage supply, labeled GND.
In normal operation, if the signal DATA is asserted, then output buffer 100 pulls the voltage on output pin 102 to the second voltage level (a low voltage level). If the signal DATA is not asserted, then output buffer 100 is placed into a high impedance or tri-state and has no effect on output pin 102. Another portion of output buffer 100 (not shown) pulls output pin 102 to the first voltage level (a high logic level) or places the second portion into a high impedance state, depending upon the signal DATA.
When output buffer 100 is off or in a high impedance state, transistor 106 is in a non-conducting state. In this case, external devices connected to output buffer 100 may couple a voltage level to output pin 102 that is either (1) greater than OVDD or (2) less than GND. Transistor 104 protects the gate-to-source voltage across transistor 106 in the case an external voltage is applied to output pin 102 that is greater than OVDD. In this case, transistor 104 clamps the voltage present on the first current electrode of transistor 106 to (OVDD-Vt), where Vt is a threshold voltage drop for an n-type transistor. Therefore, the maximum gate-to-source voltage across transistor 106 in the tri-state is (OVDD-Vt-GND) or simply (OVDD-Vt).
When output buffer 100 is active, transistor 106 may be in a non-conducting state (high logic output) or in a conducting state (low logic output). In these two cases, the maximum gate-to-source voltage across transistor 106 is (DATA-GND) or (OVDD-Vt-GND), respectively.
In certain cases, transistor 104 may itself fail. For instance, if an external device couples a voltage level to output pin 102 that is less than GND, then the gate-to-source voltage across transistor 104 will be (OVDD-GND+Vdiode), where Vdiode is the voltage drop across the parasitic diode in transistor 104. This gate-to-source voltage may exceed the maximum permissible voltage, "V.sub.GSMAX." allowed by the process technology in which output buffer 100 is fabricated.
Improvements in semiconductor process technology are constantly reducing the difference between OVDD and GND. Unfortunately, Vdiode is a characteristic of the technology that is not changing. Consequently, the gate-to-source voltage across transistor 104, (OVDD-GND+Vdiode), is being more and more influenced by Vdiode and less and less influenced by (OVDD-GND) as transistor geometries shrink.
It would be desirable to limit the gate-to-source voltage across transistor 104, (OVDD-GND+Vdiode) to a level permitted by the process technology in which output buffer 100 is fabricated. Furthermore, it would be desirable to limit the gate-to-source voltage across transistor 104 in a manner which tracks future process developments.